The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Jun. 16, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bok Eng Cheah, Gelugor, MY;

Yang Liang Poh, Bukit Mertajam, MY;

Seok Ling Lim, Kulim, MY;

Jenny Shio Yin Ong, Bayan Lepas, MY;

Jackson Chung Peng Kong, Tanjung Tokong, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/13 (2013.01); H01L 23/3164 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06558 (2013.01);
Abstract

The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.


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