The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Oct. 21, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhimin Wan, Chandler, AZ (US);

Chandra Mohan Jha, Tempe, AZ (US);

Je-Young Chang, Tempe, AZ (US);

Chia-Pin Chiu, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/15 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/15 (2013.01); H01L 23/3732 (2013.01); H01L 23/3738 (2013.01); H01L 23/49816 (2013.01); H01L 23/49861 (2013.01); H01L 24/13 (2013.01); H01L 24/29 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 2224/73103 (2013.01);
Abstract

Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.


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