The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2024
Filed:
Aug. 10, 2021
Intel Corporation, Santa Clara, CA (US);
Travis Lajoie, Forest Grove, OR (US);
Abhishek Sharma, Hillsboro, OR (US);
Juan Alzate-Vinasco, Tigard, OR (US);
Chieh-Jen Ku, Hillsboro, OR (US);
Shem Ogadhoh, Beaverton, OR (US);
Allen Gardiner, Portland, OR (US);
Blake Lin, Portland, OR (US);
Yih Wang, Portland, OR (US);
Pei-Hua Wang, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.