The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2024
Filed:
Feb. 21, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hsin-Yi Lee, Hsinchu, TW;
Weng Chang, Hsinchu, TW;
Hsiang-Pi Chang, New Taipei, TW;
Huang-Lin Chao, Hillsboro, OR (US);
Chung-Liang Cheng, Changhua County, TW;
Chi On Chui, Hsinchu, TW;
Kun-Yu Lee, Tainan, TW;
Tzer-Min Shen, Hsinchu, TW;
Yen-Tien Tung, Hsinchu, TW;
Chun-I Wu, Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.