The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2024
Filed:
Feb. 14, 2022
Intel Corporation, Santa Clara, CA (US);
Manish Chandhok, Beaverton, OR (US);
Leonard Guler, Hillsboro, OR (US);
Paul Nyhus, Portland, OR (US);
Gobind Bisht, Portland, OR (US);
Jonathan Laib, Portland, OR (US);
David Shykind, Buxton, OR (US);
Gurpreet Singh, Portland, OR (US);
Eungnak Han, Portland, OR (US);
Noriyuki Sato, Hillsboro, OR (US);
Charles Wallace, Portland, OR (US);
Jinnie Aloysius, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.