The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2024

Filed:

Jul. 14, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Kuei Hsu, Hsinchu, TW;

Ming-Chih Yew, Hsinchu, TW;

Shu-Shen Yeh, Taoyuan, TW;

Che-Chia Yang, Taipei, TW;

Po-Yao Lin, Zhudong Township, TW;

Shin-Puu Jeng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/20 (2013.01); H01L 24/30 (2013.01); H01L 24/82 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/072 (2013.01); H01L 21/486 (2013.01); H01L 23/3128 (2013.01);
Abstract

An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.


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