The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Dec. 21, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Noriyuki Sato, Hillsboro, OR (US);

Sarah Atanasov, Beaverton, OR (US);

Abhishek A. Sharma, Portland, OR (US);

Bernhard Sell, Portland, OR (US);

Chieh-Jen Ku, Hillsboro, OR (US);

Elliot N. Tan, Portland, OR (US);

Hui Jae Yoo, Portland, OR (US);

Travis W. Lajoie, Forest Grove, OR (US);

Van H. Le, Portland, OR (US);

Pei-Hua Wang, Beaverton, OR (US);

Jason Peck, Hillsboro, OR (US);

Tobias Brown-Heft, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/823431 (2013.01); H01L 27/0924 (2013.01);
Abstract

Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.


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