The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2024
Filed:
Sep. 26, 2019
Intel Corporation, Santa Clara, CA (US);
Travis W. Lajoie, Forest Grove, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Juan G. Alzate Vinasco, Tigard, OR (US);
Chieh-Jen Ku, Hillsboro, OR (US);
Shem O. Ogadhoh, Beaverton, OR (US);
Allen B. Gardiner, Portland, OR (US);
Blake C. Lin, Portland, OR (US);
Yih Wang, Portland, OR (US);
Pei-Hua Wang, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.