The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

May. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jiun-Ting Chen, Hsinchu, TW;

Ying-Ching Shih, Hsinchu, TW;

Szu-Wei Lu, Hsinchu, TW;

Chih-Wei Wu, Zhuangwei Township, Yilan County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/563 (2013.01); H01L 23/3157 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.


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