The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Jun. 18, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Meng-Ku Chen, New Taipei, TW;

Ji-Yin Tsai, Zhudong Township, TW;

Jeng-Wei Yu, New Taipei, TW;

Yi-Fang Pai, Hsinchu, TW;

Pei-Ren Jeng, Chu-Bei, TW;

Yee-Chia Yeo, Hsinchu, TW;

Chii-Horng Li, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/82345 (2013.01); H01L 29/0642 (2013.01); H01L 29/1083 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/785 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01);
Abstract

A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.


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