The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Sep. 18, 2020
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
William Hsu, Hillsboro, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
Martin Weiss, Portland, OR (US);
Apratim Dhar, Portland, OR (US);
William T. Blanton, Cornelius, OR (US);
John H. Irby, IV, Hillsboro, OR (US);
James F. Bondi, Beaverton, OR (US);
Michael K. Harper, Hillsboro, OR (US);
Charles H. Wallace, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Benedict A. Samuel, Hillsboro, OR (US);
Stefan Dickert, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.