The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2024
Filed:
Jul. 30, 2021
Globalfoundries U.s. Inc., Malta, NY (US);
Zhong-Xiang He, Essex Junction, VT (US);
Richard J. Rassel, Essex Junction, VT (US);
Alvin J. Joseph, Williston, VT (US);
Ramsey M. Hazbun, Colchester, VT (US);
Jeonghyun Hwang, Ithaca, NY (US);
Mark D. Levy, Williston, VT (US);
GlobalFoundries U.S. Inc., Malta, NY (US);
Abstract
Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.