The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

Jun. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hung-Chang Sun, Kaohsiung, TW;

Po-Chin Chang, Taichung, TW;

Akira Mineji, Hsinchu County, TW;

Zi-Wei Fang, Hsinchu County, TW;

Pinyen Lin, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76837 (2013.01); H01L 21/76804 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76825 (2013.01); H01L 21/76829 (2013.01); H01L 21/76895 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 23/53295 (2013.01); H01L 23/535 (2013.01); H01L 27/088 (2013.01);
Abstract

A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.


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