The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2024
Filed:
Jul. 27, 2020
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Shou Zen Chang, Taipei County, TW;
Chun-Lin Lu, Hsinchu, TW;
Kai-Chiang Wu, Hsinchu, TW;
Ching-Feng Yang, Taipei, TW;
Vincent Chen, Taipei, TW;
Chuei-Tang Wang, Taichung, TW;
Yen-Ping Wang, Changhua County, TW;
Hsien-Wei Chen, Hsinchu, TW;
Wei-Ting Lin, Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.