The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2024
Filed:
Dec. 09, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Seiji Takahashi, Hsinchu, TW;
Chen-Jong Wang, Hsin-Chu, TW;
Dun-Nian Yaung, Taipei, TW;
Feng-Chi Hung, Chu-Bei, TW;
Feng-Jia Shiu, Jhudong Township, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Jhy-Jyi Sze, Hsin-Chu, TW;
Chun-Wei Chang, Tainan, TW;
Wei-Cheng Hsu, Kaohsiung, TW;
Wei Chuang Wu, Tainan, TW;
Yimin Huang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.