The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Sep. 25, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jieying Kong, Chandler, AZ (US);

Yiyang Zhou, Chandler, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Jeremy Ecton, Gilbert, AZ (US);

Hongxia Feng, Chandler, AZ (US);

Tarek Ibrahim, Mesa, AZ (US);

Brandon Marin, Chandler, AZ (US);

Zhiguo Qian, Chandler, AZ (US);

Sarah Blythe, Chandler, AZ (US);

Bohan Shan, Chandler, AZ (US);

Jason Steill, Phoenix, AZ (US);

Sri Chaitra Jyotsna Chavali, Chandler, AZ (US);

Leonel Arana, Phoenix, AZ (US);

Dingying Xu, Chandler, AZ (US);

Marcel Wall, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/485 (2013.01); H01L 23/49827 (2013.01);
Abstract

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.


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