The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Nov. 05, 2019
Applicants:

Kwansei Gakuin Educational Foundation, Hyogo, JP;

Toyota Tsusho Corporation, Nagoya, JP;

Inventors:

Tadaaki Kaneko, Hyogo, JP;

Koji Ashida, Hyogo, JP;

Tomoya Ihara, Hyogo, JP;

Daichi Dojima, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 29/36 (2006.01); C30B 23/02 (2006.01); C30B 25/20 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02529 (2013.01); C30B 23/02 (2013.01); C30B 25/20 (2013.01); C30B 29/36 (2013.01); H01L 21/02428 (2013.01); H01L 21/02612 (2013.01);
Abstract

An object of the present invention is to provide a SiC semiconductor substrate capable of reducing a density of basal plane dislocations (BPD) in a growth layer, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a strained layer removal process Sthat removes a strained layer introduced on a surface of a SiC substrate; and an epitaxial growth process Sthat conducts growth under a condition that a terrace width W of the SiC substrate is increased. When a SiC semiconductor substrate is manufactured in such processes, the basal plane dislocations BPD in the growth layer can be reduced, and a yield of a SiC semiconductor device can be improved.


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