The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
Apr. 21, 2022
Intel Corporation, Santa Clara, CA (US);
Aaron D. Lilak, Beaverton, OR (US);
Anh Phan, Beaverton, OR (US);
Ehren Mannebach, Tigard, OR (US);
Cheng-Ying Huang, kPortland, OR (US);
Stephanie A. Bojarski, Beaverton, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Orb Acton, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.