The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2024
Filed:
Feb. 07, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Pin-Dai Sue, Hsinchu, TW;
Po-Hsiang Huang, Hsinchu, TW;
Fong-Yuan Chang, Hsinchu, TW;
Chi-Yu Lu, Hsinchu, TW;
Sheng-Hsiung Chen, Hsinchu, TW;
Chin-Chou Liu, Hsinchu, TW;
Lee-Chung Lu, Hsinchu, TW;
Yen-Hung Lin, Hsinchu, TW;
Li-Chun Tien, Hsinchu, TW;
Yi-Kan Cheng, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.