The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Dec. 01, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Chang Soo Suh, Allen, TX (US);

Jungwoo Joh, Allen, TX (US);

Dong Seup Lee, McKinney, TX (US);

Shoji Wada, McKinney, TX (US);

Karen Hildegard Ralston Kirmse, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); B82Y 30/00 (2011.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); B82Y 30/00 (2013.01); B82Y 40/00 (2013.01);
Abstract

A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.


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