The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2024
Filed:
May. 16, 2022
Intel Corporation, Santa Clara, CA (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Jack Kavalieros, Portland, OR (US);
Ian Young, Portland, OR (US);
Matthew Metz, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Uygar Avci, Portland, OR (US);
Ashish Agrawal, Hillsboro, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.