The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Jan. 31, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chin-Chieh Yang, New Taipei, TW;

Hsia-Wei Chen, Taipei, TW;

Chih-Yang Chang, Yualin Township, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Wen-Ting Chu, Kaohsiung, TW;

Yu-Wen Liao, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H01L 29/66 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H10B 63/30 (2023.02); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 29/0847 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H10N 70/011 (2023.02); H10N 70/026 (2023.02); H10N 70/20 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/883 (2023.02); H10N 70/8833 (2023.02);
Abstract

A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.


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