The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Jan. 12, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc Nanjing Company, Limited, Nanjing, CN;
Hidehiro Fujiwara, Hsinchu, TW;
Tze-Chiang Huang, Hsinchu, TW;
Hong-Chen Cheng, Hsinchu, TW;
Yen-Huei Chen, Hsinchu, TW;
Hung-Jen Liao, Hsinchu, TW;
Jonathan Tsung-Yung Chang, Hsinchu, TW;
Yun-Han Lee, Hsinchu, TW;
Lee-Chung Lu, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC NANJING COMPANY, LIMITED, Nanjing, CN;
Abstract
An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.