The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Dec. 12, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ying-Cheng Tseng, Tainan, TW;

Yu-Chih Huang, Hsinchu, TW;

Chih-Hsuan Tai, Taipei, TW;

Ting-Ting Kuo, Hsinchu, TW;

Chi-Hui Lai, Taichung, TW;

Ban-Li Wu, Hsinchu, TW;

Chiahung Liu, Hsinchu, TW;

Hao-Yi Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 21/70 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/013 (2013.01); H01L 21/705 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 24/13 (2013.01); H01L 28/10 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 25/105 (2013.01); H01L 2224/13025 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.


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