The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

Jun. 29, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

Hung-Jui Kuo, Hsinchu, TW;

Ming-Che Ho, Tainan, TW;

Tzung-Hui Lee, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/481 (2013.01); H01L 23/485 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/83 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 25/105 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13149 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13166 (2013.01); H01L 2224/13184 (2013.01); H01L 2224/18 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83815 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/181 (2013.01);
Abstract

An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.


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