The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2023
Filed:
Jun. 28, 2019
Intel Corporation, Santa Clara, CA (US);
Travis W. Lajoie, Forest Grove, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Van H. Le, Portland, OR (US);
Chieh-Jen Ku, Hillsboro, OR (US);
Pei-Hua Wang, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Gregory George, Beaverton, OR (US);
Akash Garg, Portland, OR (US);
Allen B. Gardiner, Portland, OR (US);
Shem Ogadhoh, Beaverton, OR (US);
Juan G. Alzate Vinasco, Tigard, OR (US);
Umut Arslan, Portland, OR (US);
Fatih Hamzaoglu, Portland, OR (US);
Nikhil Mehta, Portland, OR (US);
Jared Stoeger, Portland, OR (US);
Yu-Wen Huang, Beaverton, OR (US);
Shu Zhou, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.