The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2023
Filed:
Aug. 19, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Yao-Wen Chang, Taipei, TW;
Chung-Chiang Min, Zhubei, TW;
Harry-Hak-Lay Chuang, Zhubei, TW;
Hung Cho Wang, Taipei, TW;
Tsung-Hsueh Yang, Taichung, TW;
Yuan-Tai Tseng, Zhubei, TW;
Sheng-Huang Huang, Hsinchu, TW;
Chia-Hua Lin, New Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.