The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Sep. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chieh-Fei Chiu, Tainan, TW;

Wen-Ting Chu, Kaohsiung, TW;

Yong-Shiuan Tsair, Tainan, TW;

Yu-Wen Liao, New Taipei, TW;

Chih-Yang Chang, Changhua County, TW;

Chin-Chieh Yang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H10B 63/00 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/30 (2023.02); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/068 (2023.02); H10N 70/231 (2023.02); H10N 70/253 (2023.02); H10N 70/841 (2023.02);
Abstract

A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.


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