The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Sep. 30, 2022
Applicant:

Deca Technologies Usa, Inc., Tempe, AZ (US);

Inventors:

Robin Davis, Vancouver, WA (US);

Paul R. Hoffman, San Diego, CA (US);

Clifford Sandstrom, Richfield, MN (US);

Timothy L. Olson, Phoenix, AZ (US);

Assignee:

Deca Technologies USA, Inc., Tempe, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4839 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/81411 (2013.01); H01L 2224/81424 (2013.01); H01L 2224/81439 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/81457 (2013.01); H01L 2224/81466 (2013.01); H01L 2224/81469 (2013.01); H01L 2224/81481 (2013.01); H01L 2224/81484 (2013.01);
Abstract

A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.


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