The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Jun. 05, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ting Fang, Kaohsiung, TW;

Da-Wen Lin, Hsinchu, TW;

Fu-Kai Yang, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/423 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01); H01L 29/456 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.


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