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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11728265 B1

PDFFull Text
Date of Patent:
Aug. 15, 2023

Filed:

Sep. 12, 2018

Selective deposition of embedded thin-film resistors for semiconductor packaging

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Brandon C. Marin, Chandler, AZ (US);

Frank Truong, Gilbert, AZ (US);

Shivasubramanian Balasubramanian, Gilbert, AZ (US);

Dilan Seneviratne, Chandler, AZ (US);

Yonggang Li, Chandler, AZ (US);

Sameer Paital, Chandler, AZ (US);

Darko Grujicic, Chandler, AZ (US);

Rengarajan Shanmugam, Chandler, AZ (US);

Melissa Wette, East Palo Alto, CA (US);

Srinivas Pietambaram, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt P.C.

Primary Examiner:

Daniel Luke

Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 27/01 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 21/4846 (2013.01); H01L 21/76871 (2013.01); H01L 23/498 (2013.01); H01L 23/5226 (2013.01); H01L 23/647 (2013.01); H01L 24/09 (2013.01); H01L 27/016 (2013.01); H01L 28/24 (2013.01);
Abstract

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

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