The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2023
Filed:
Jun. 11, 2019
Intel Corporation, Santa Clara, CA (US);
Andrew J. Brown, Gilbert, AZ (US);
Luke Garner, Chandler, AZ (US);
Liwei Cheng, Chandler, AZ (US);
Lauren Link, Mesa, AZ (US);
Cheng Xu, Chandler, AZ (US);
Ying Wang, Chandler, AZ (US);
Bin Zou, Chandler, AZ (US);
Chong Zhang, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.