The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2023
Filed:
Jun. 23, 2021
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hui Yu Lee, Hsin-Chu, TW;
Chin-Chou Liu, Jhubei, TW;
Cheng-Hung Yeh, Jhunan Township, TW;
Fong-Yuan Chang, Hsin-Chu, TW;
Po-Hsiang Huang, Tainan, TW;
Yi-Kan Cheng, Taipei, TW;
Ka Fai Chang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line. The MIM capacitor includes (i) a top capacitor electrode in the first dielectric layer and electrically coupled to the second conducting line; (ii) a bottom capacitor electrode in the first dielectric layer and above the first conducting line, wherein the bottom capacitor electrode is configured to be electrically floating; and (iii) a second dielectric layer between the top and bottom capacitor electrodes.