The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Apr. 20, 2021
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

John Hon-Shing Lau, Taoyuan, TW;

Cheng-Ta Ko, Taipei, TW;

Pu-Ju Lin, Hsinchu, TW;

Chi-Hai Kuo, Taoyuan, TW;

Kai-Ming Yang, Hsinchu County, TW;

Chia-Yu Peng, Taoyuan, TW;

Shao-Chien Lee, Taipei, TW;

Tzyy-Jang Tseng, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 1/16 (2006.01); H05K 1/18 (2006.01); H05K 3/20 (2006.01); H05K 3/36 (2006.01); H05K 3/38 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01); H05K 3/02 (2006.01);
U.S. Cl.
CPC ...
H05K 3/46 (2013.01); H05K 3/022 (2013.01); H05K 3/386 (2013.01); H05K 3/4038 (2013.01);
Abstract

A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.


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