The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Jun. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin Lai Lin, Beaverton, OR (US);

Manish Chandhok, Beaverton, OR (US);

Miriam Reshotko, Portland, OR (US);

Christopher Jezewski, Portland, OR (US);

Eungnak Han, Portland, OR (US);

Gurpreet Singh, Portland, OR (US);

Sarah Atanasov, Beaverton, OR (US);

Ian A. Young, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5222 (2013.01); H01L 21/76802 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01);
Abstract

An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.


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