The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Jun. 23, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shu-Wei Li, Hsinchu, TW;

Shin-Yi Yang, New Taipei, TW;

Ming-Han Lee, Taipei, TW;

Shau-Lin Shue, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/02063 (2013.01); H01L 21/7682 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01);
Abstract

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.


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