The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2023
Filed:
Oct. 19, 2020
Intel Corporation, Santa Clara, CA (US);
Van H. Le, Beaverton, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Rafael Rios, Austin, TX (US);
Jack T. Kavalieros, Portland, OR (US);
Marko Radosavljevic, Portland, OR (US);
Kent E. Millard, Hillsboro, OR (US);
Marc C. French, Forest Grove, OR (US);
Ashish Agrawal, Hillsboro, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Ryan E. Arch, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.