The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2023

Filed:

Dec. 16, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Liang Chen, Hinchu, TW;

Chih-Ming Lai, Hsinchu, TW;

Charles Chew-Yuen Young, Hsinchu, TW;

Chin-Yuan Tseng, Hsinchu, TW;

Jiann-Tyng Tzeng, Hsinchu, TW;

Kam-Tou Sio, Hsinchu, TW;

Ru-Gun Liu, Hsinchu, TW;

Wei-Liang Lin, Hsinchu, TW;

L. C. Chou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/11 (2006.01); H01L 27/088 (2006.01); H01L 21/308 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/3083 (2013.01); H01L 21/3086 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/31144 (2013.01);
Abstract

In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.


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