The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2023

Filed:

Apr. 07, 2021
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventors:

Changhung Kung, Shanghai, CN;

Xiantao Li, Shanghai, CN;

Xiumei Hu, Shanghai, CN;

Jianxun Chen, Shanghai, CN;

Chanyuan Hu, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02269 (2013.01); H01L 21/02274 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 29/401 (2013.01);
Abstract

A method for manufacturing a semiconductor device comprising: providing a substrate, wherein an amorphous silicon layer is formed on the substrate; forming an etching auxiliary layer on the amorphous silicon layer, wherein the upper surface of the etching auxiliary layer is flat, and the etching auxiliary layer is made of a single material; and etching the amorphous silicon layer and the etching auxiliary layer to obtain an amorphous silicon layer with a target thickness, wherein the upper surface of the etched amorphous silicon layer is flat.


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