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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11594673 B1

PDFFull Text
Date of Patent:
Feb. 28, 2023

Filed:

Mar. 27, 2019

Two terminal spin orbit memory devices and methods of fabrication

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Noriyuki Sato, Hillsboro, OR (US);

Angeline Smith, Hillsboro, OR (US);

Tanay Gosavi, Hillsboro, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Kaan Oguz, Portland, OR (US);

Kevin O'Brien, Portland, OR (US);

Benjamin Buford, Hillsboro, OR (US);

Tofizur Rahman, Portland, OR (US);

Rohan Patil, Hillsboro, OR (US);

Nafees Kabir, Portland, OR (US);

Michael Christenson, Santa Clara, CA (US);

Ian Young, Portland, OR (US);

Hui Jae Yoo, Hillsboro, OR (US);

Christopher Wiegand, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Essential Patents Group, LLP

Primary Examiner:

David Vu

Assistant Examiner:

Brandon C Fox

Int. Cl.
CPC ...
H01F 10/32 (2006.01); H01L 43/10 (2006.01); G11C 11/16 (2006.01); H01L 43/02 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01); H01F 41/34 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); H01F 10/329 (2013.01); H01L 27/228 (2013.01); H01L 43/10 (2013.01); H01F 10/3254 (2013.01); H01F 10/3272 (2013.01); H01F 10/3286 (2013.01); H01F 41/34 (2013.01); H01L 43/12 (2013.01);
Abstract

A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

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