The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

Dec. 29, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Boon Yew Low, Subang Jaya, MY;

Fernando A. Santos, Chandler, AZ (US);

Li Li, Scottsdale, AZ (US);

Fui Yee Lim, Kuala Lumpur, MY;

Lan Chu Tan, Singapore, SG;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/42 (2006.01); H01L 21/48 (2006.01); H01L 23/482 (2006.01);
U.S. Cl.
CPC ...
H01L 23/42 (2013.01); H01L 21/4871 (2013.01); H01L 23/4824 (2013.01);
Abstract

A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.


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