The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2023
Filed:
Jun. 04, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Pin-Dai Sue, Hsinchu, TW;
Po-Hsiang Huang, Hsinchu, TW;
Fong-Yuan Chang, Hsinchu, TW;
Chi-Yu Lu, Hsinchu, TW;
Sheng-Hsiung Chen, Hsinchu, TW;
Chin-Chou Liu, Hsinchu, TW;
Lee-Chung Lu, Hsinchu, TW;
Yen-Hung Lin, Hsinchu, TW;
Li-Chun Tien, Hsinchu, TW;
Yi-Kan Cheng, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.