The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2023
Filed:
Dec. 29, 2017
Intel Corporation, Santa Clara, CA (US);
Andrew P. Collins, Chandler, AZ (US);
Digvijay A. Raorane, Chandler, AZ (US);
Wilfred Gomes, Portland, OR (US);
Ravindranath V. Mahajan, Chandler, AZ (US);
Sujit Sharan, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridgeoccupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.