The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Jan. 16, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Hung Chu, Taipei, TW;

Sung-Li Wang, Zhubei, TW;

Fang-Wei Lee, Hsinchu, TW;

Jung-Hao Chang, Taichung, TW;

Mrunal Abhijith Khaderbad, Hsinchu, TW;

Keng-Chu Lin, Ping-Tung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/45 (2006.01); H01L 21/311 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/308 (2006.01); H01L 21/027 (2006.01); H01L 21/3065 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/31116 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/66795 (2013.01); H01L 21/0274 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.


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