The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2022
Filed:
Apr. 20, 2021
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Tsmc China Company, Limited, Songjiang, CN;
Yi-Tzu Chen, Hsinchu, TW;
Ching-Wei Wu, Hsinchu, TW;
Hau-Tai Shieh, Hsinchu, TW;
Hung-Jen Liao, Hsinchu, TW;
Fu-An Wu, Hsinchu, TW;
He-Zhou Wan, Hsinchu, TW;
XiuLi Yang, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC CHINA COMPANY, LIMITED, Shanghai, CN;
Abstract
A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.