The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Jun. 27, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Seiyon Kim, Portland, OR (US);

Gopinath Bhimarasetti, Portland, OR (US);

Rafael Rios, Austin, TX (US);

Jack T. Kavalieros, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Rishabh Mehandru, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 23/498 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02233 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/1037 (2013.01); H01L 29/1083 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 21/02546 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 29/0847 (2013.01);
Abstract

A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.


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