The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Apr. 03, 2017
Applicant:

Nepes Co., Ltd., Chungcheongbuk-do, KR;

Inventors:

Yong-Tae Kwon, Cheongju-si, KR;

Jun-Kyu Lee, Cheongju-si, KR;

Si Woo Lim, Daegu, KR;

Dong-Hoon Oh, Seoul, KR;

Jun-Sung Ma, Seoul, KR;

Tae-Won Kim, Cheongju-si, KR;

Assignee:

NEPES CO., LTD., Chungcheongbuk-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/552 (2006.01); H01L 23/522 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 21/56 (2013.01); H01L 21/563 (2013.01); H01L 21/6835 (2013.01); H01L 23/31 (2013.01); H01L 23/498 (2013.01); H01L 23/522 (2013.01); H01L 23/525 (2013.01); H01L 23/552 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73104 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83856 (2013.01); H01L 2224/83986 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.


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