The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Jul. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chen-Liang Chu, Hsin-Chu, TW;

Chien-Chih Chou, New Taipei, TW;

Chih-Chang Cheng, Hsinchu, TW;

Yi-Huan Chen, Hsin Chu, TW;

Kong-Beng Thei, Pao-Shan Village, TW;

Ming-Ta Lei, Hsin-Chu, TW;

Ruey-Hsin Liu, Hsin-Chu, TW;

Ta-Yuan Kung, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/28114 (2013.01); H01L 21/28518 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/4238 (2013.01); H01L 29/45 (2013.01); H01L 29/4983 (2013.01); H01L 29/66492 (2013.01); H01L 29/7833 (2013.01);
Abstract

A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.


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