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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11437379 B1

PDFFull Text
Date of Patent:
Sep. 06, 2022

Filed:

Sep. 18, 2020

Field-effect transistors (fet) circuits employing topside and backside contacts for topside and backside routing of fet power and logic signals, and related complementary metal oxide semiconductor (cmos) circuits

Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Stanley Seungchul Song, San Diego, CA (US);

Deepak Sharma, Bangalore, IN;

Bharani Chava, Cork, BE;

Hyeokjin Lim, San Diego, CA (US);

Peijie Feng, San Diego, CA (US);

Seung Hyuk Kang, San Diego, CA (US);

Jonghae Kim, San Diego, CA (US);

Periannan Chidambaram, San Diego, CA (US);

Kern Rim, San Diego, CA (US);

Giridhar Nallapati, San Diego, CA (US);

Venugopal Boynapalli, San Diego, CA (US);

Foua Vang, Sacramento, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:

Qualcomm Incorporated

Primary Examiner:

Calvin Lee

Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 27/095 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H01L 27/095 (2013.01); H01L 23/5286 (2013.01); H01L 29/7851 (2013.01); H03K 19/018521 (2013.01); H01L 2029/7858 (2013.01);
Abstract

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

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