The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2022
Filed:
Jun. 15, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Yi-Wen Wu, Xizhi, TW;
Po-Yao Chuang, Hsinchu, TW;
Meng-Liang Lin, Hsinchu, TW;
Techi Wong, Zhubei, TW;
Shih-Ting Hung, Sanchong, TW;
Po-Hao Tsai, Zhongli, TW;
Shin-Puu Jeng, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 24/16 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 25/18 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24155 (2013.01); H01L 2224/2505 (2013.01); H01L 2224/25171 (2013.01);
Abstract
Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.